The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a word line driver for driving word lines.
There are demands to improve the integration density of semiconductor memory devices, and attempts have been made to reduce the size of unit elements forming a semiconductor memory device such as a dynamic random access memory device (DRAM). In order to reduce the size of the unit element, that is, the dynamic memory cell, it is possible to take measures such as reducing the gate length, reducing the thickness of the gate oxide layer and reducing the width of the device isolation.
When the gate length or the thickness of the gate oxide layer is reduced, it is necessary to reduce the voltage which is applied to the element proportionally to the scaling rule.
However, a circuit such as the word decoder of the semiconductor memory device must have a sufficiently high withstand voltage because a relatively large voltage is applied to such a circuit. For this reason, there is a limit to reducing the gate length and the device isolation in such a circuit.
On the other hand, when reducing the size of the cell, it is also necessary to reduce the interval of the word lines. Accordingly, in the case of the word decoder which selects word lines, for example, it becomes necessary to reduce the width of the unit circuit of the word driver columns forming the word decoder depending on the interval of the word lines.
Next, a description will be given of an example of a word line driver of a conventional semiconductor memory device, by referring to FIGS. 1 through 3. FIG. 1 shows the word line driver in a plan view, FIG. 2 shows the word line driver in a cross section taken along a line A--A in FIG. 1, and FIG. 3 shows the word line driver in a cross section taken along a line B--B in FIG. 1.
The word line driver shown in FIG. 1 is provided with two boost signal lines 100 and 200 because this word line driver uses a word line activation signal which is predecoded with respect to the word decoder. The word line driver is made up of N-channel metal oxide semiconductor (MOS) transistors.
Word lines 50, 52, 54, 56, 58 and 60 for outputting signals to a memory cell array (not shown) extend parallel to each other. The boost signal lines 100 and 200 extend perpendicularly to these word lines 50 through 60.
In a region between the two boost signal lines 100 and 200, device isolation regions 7, 7' and 7" are formed in parallel to the word lines 50 through 60. The device isolation region 7 is formed between the word lines 54 and 56, the device isolation region 7' is formed between the word lines 50 and 52, and the device isolation region 7" is formed between the word lines 58 and 60. Element regions 8, 8', 9 and 9' extend in parallel to the word lines 50 through 60. The device isolation 7' isolates the element regions 8 an 9', the device isolation 7 isolates the element regions 8 and 9, and the device isolation 7" isolates the element regions 8' and 9. A driver 1 is formed within the element region 9', drivers 2 and 3 are formed within the element region 8, drivers 4 and 5 are formed within the element region 9, and a driver 6 is formed within the element region 8'. Each of the drivers 1 through 6 are made up of MOS field effect transistors (MOSFETs) respectively having a gate electrode formed between a source region and a drain region.
The driver 2 includes a drain region 32 for inputting a word line activation signal from the boost signal line 100, a gate electrode 80, and a source region 20 which is coupled to the word line 50 via a word line contact 12. The driver 3 includes a drain region 32 for inputting a word line activation signal from the boost signal line 100, a gate electrode 82, and a source region 21 which is coupled to the word line 54 via a word line contact 10. The driver 6 includes a drain region 36 for inputting a word line activation signal from the boost signal line 100, a gate electrode 84, and a source region 22 which is coupled to the word line 58 via a word line contact 13. The drain region 32 which is connected to the boost signal line 100 is used in common by the drivers 2 and 3, as shown in FIGS. 2 and 3.
On the other hand, the driver 1 includes a drain region 38 for inputting a word line activation signal from the boost signal line 200, a gate electrode 86 and a source region 23 which is coupled to the word line 52 via a word line contact 14. The driver 4 includes a drain region 42 for inputting a word line activation signal from the boost signal line 200, a gate electrode 88, and a source region 24 which is coupled to the word line 56 via a word line contact 11. The driver 5 includes a drain region 42 for inputting a word line activation signal from the boost signal line 200, a gate electrode 90, and a source region 25 which is coupled to the word line 60 via a word line contact 15. The drain region 42 which is connected to the boost signal line 200 is used in common by the drives 4 and 5, as shown in FIGS. 2 and 3.
The word lines 50 through 60 are respectively coupled to the memory cell array (not shown) which is provided above the boost signal line 100 in FIG. 1. On the other hand, a decoder (not shown) is provided below the boost signal line 200 in FIG. 1.
The gate electrode 86 of the driver 1 and the gate electrode 80 of the driver 2 are connected in common to a signal line 70 from the decoder. The gate electrode 82 of the driver 3 and the gate electrode 88 of the driver 4 are connected in common to a signal line 72 from the decoder. In addition, the gate electrode 90 of the driver 5 and the gate electrode 84 of the driver 6 are connected in common to a signal line 74 from the decoder.
Because the word line driver has the structure described above, it is possible to control two word lines using one decoder. In this specification, a width occupied by the drivers used by one decoder will be referred to as "one decoder pitch". Accordingly, it is possible to further reduce the size of the elements if this "one decoder pitch" can be reduced.
In order to guarantee a sufficient withstand voltage between the elements with respect to the voltage applied to the boost signal lines 100 and 200, it is necessary to provide the device isolation region 7 between the word lines 54 and 56 which respectively transfer outputs of the drivers 3 and 4. The width of this device isolation region 7 along the direction in which the "one decoder pitch" is taken must be sufficiently large such that a sufficient withstand voltage is guaranteed between the elements. For this reason, there are problems in that the gate length of the drivers 3 and 4 cannot be set sufficiently large with respect to the voltage applied to the boost signal lines 100 and 200, and that the source-drain withstand voltage of the drivers 3 and 4 becomes poor.
On the other hand, when the gate length of the drivers 3 and 4 is set sufficiently large with respect to the voltage applied to the boost signal lines 100 and 200, there are problems in that the width of the device isolation region 7 along the direction in which the "one decoder pitch" is taken cannot be made sufficiently large with respect to the voltage applied to the boost signal lines 100 and 200, and that the withstand voltage of the element becomes poor. Therefore, a problem is introduced from the point of view of the reliability of the elements, and this problem becomes more serious as the size of the elements is further reduced.